Exemplary embodiments of the present invention relate generally to an internal voltage generation circuit which may be applied to a semiconductor integrated circuit including a plurality of banks.
In general, a semiconductor integrated circuit is supplied with a power supply voltage (VDD) and a ground voltage (VSS) from an outside and generates therein internal voltages used to perform internal operations. The internal voltages used to perform the internal operations of the semiconductor integrated circuit may include a core voltage (VCORE) supplied to a memory core region, a high voltage (VPP) used when driving a word line or upon overdriving, a back-bias voltage (VBB) supplied as a bulk voltage of an NMOS transistor of a core region, and so forth.
Here, the core voltage (VCORE) may be supplied by reducing the power supply voltage (VDD) inputted from the outside. However, the high voltage (VPP) has a level higher than the power supply voltage (VDD) inputted from the outside, and the back-bias voltage (VBB) has a level lower than the ground voltage (VSS) inputted from the outside. Therefore, in order to supply the high voltage (VPP) and the back-bias voltage (VBB), a charge pump circuit generating power sources such as the high voltage (VPP) or the back-bias voltage (VBB) may be used.
Further, with the degree of high integration of a semiconductor integrated, more banks may be included in the semiconductor integrated circuit. Internal voltages are supplied, for example, only to banks which perform a read operation or a write operation. Accordingly, in order to supply internal voltages to corresponding banks, a plurality of internal voltage generation circuits may be provided in the semiconductor integrated circuit.
FIG. 1 is a timing diagram showing operations of a known internal voltage generation circuit.
Referring to FIG. 1, there are shown operations of an internal voltage generation circuit for supplying internal voltages to a first bank (not shown) and a second bank (not shown) included in a semiconductor integrated circuit. In FIG. 1, in the case where a read operation and a write operation are sequentially performed for the first bank and the second bank, the internal voltage generation circuit is activated by receiving an enable pulse ENP which is enabled to a logic high level in synchronization with a first bank active signal RACT<1>, and supplies internal voltages to the first and second banks. Thereafter, if the read operation and the write operation for the first and second banks are all completed and both the first bank active signal RACT<1> and a second bank active signal RACT<2> have a logic low level, the internal voltage generation circuit is deactivated by receiving the enable pulse ENP which is disabled to a logic low level and interrupts the supply of the internal voltages to the first and second banks. The first bank active signal RACT<1> is enabled to a logic high level when the read operation or the write operation is performed for the first bank, and the second bank active signal RACT<2> is enabled to a logic high level when the read operation or the write operation is performed for the second bank.
As the number of banks increases with the degree of high integration of a semiconductor integrated circuit, the number of control signals for controlling the activation of the internal voltage generation circuits increases. For example, the number of the internal voltage generation circuits in a semiconductor integrated circuit, such as DDR4 SDRAM including 16 banks therein, may be twice as many as that of a semiconductor integrated circuit including 8 banks therein. Also, the number of control signals for controlling the internal voltage generation circuits in the semiconductor integrated circuit such as the DDR4 SDRAM including 16 banks therein may be twice as many as that of a semiconductor integrated circuit including 8 banks therein.
Because a write operation needs to drive a write driver and a local input/output line, the write operation may consume more internal voltages than a read operation. However, in the known internal voltage generation circuit, the internal voltage generation circuit is activated during the same period and supplies the internal voltages in the write and read operations. Accordingly, the internal voltages may not be sufficiently supplied during the write operation and the internal voltages may be excessively supplied during the read operation.